Embodiments of the inventive concepts relate generally to a semiconductor device and/or methods of fabrication, and more particularly, to semiconductor devices having through electrodes or conductive via structure and/or to methods of fabricating the same.
A process of fabricating a semiconductor device with a through electrode or a through silicon via (TSV) may include protruding the through electrode outward from a bottom surface of a substrate, depositing a conventional chemical vapor deposition (CVD) layer on the bottom surface of the substrate, and then exposing the through electrode using a chemical-mechanical polishing process. The conventional CVD layer may have a poor step coverage property. For example, the conventional CVD layer may be formed to be thicker on the through electrode than on other portions. As a result, a lower insulating layer may be folded and the through electrode may be formed to have a high variation in protruding length thereof. Theses may lead to warpage or breakage of the through electrode in a subsequent planarization process, and thus a production yield may decrease.